1. Field of the Invention
The present invention relates to a circuit applicable to a semiconductor memory device, and in particular, to a decoder circuit which is capable of generating a redundancy signal having a short pulse format, and controlled by the generated signal.
2. Description of the Related Art
Conventionally, a volatile semiconductor memory device has a redundancy repairing scheme for disabling a normal word line or a column pass by use of a signal. A word line redundancy repairing scheme controls an enabling operation or a disabling operation of a section word line decoder by applying a redundancy signal to the section word line decoder which receives a main word line signal, and then in turn generates a signal to select a section word line.
In the prior art, however, it is difficult to rapidly perform the enabling operation of the normal word line because of a static transition of the redundancy signal, which increases the signal load and/or slows the transition speed. FIG. 1 showing timing diagram having clock XCK illustrates the redundancy cycle of the prior art. The enabling speed of a cycle 22A proceeded by a redundancy cycle 101 of the normal word line in the prior art is reduced by that proceeding redundancy cycle 101 itself. That is, here, the enabling speed of the normal word line 22A is interrupted via a line path 1. As a result, because of increase of the load or a reduction of a transition speed, the prior art has a disadvantage in that an enabling speed of a normal word line 22A is easily interrupted.
In the prior art as shown in FIG. 2, a row redundancy address decoder 300, more specifically includes a programmable fuse box 301 and lines 10 and 11 for providing a redundancy main word line signal and a redundancy signal respectively. Row redundancy address decoder 300 includes inverters 302 and 303 and node "A" which is transited from the logic "low" level state to the logic "high" level state during redundancy access, that is node "A" is enabled to the "high" level state during the redundancy access.
In the above redundancy repairing scheme, a redundancy word line of an address to be repaired or a redundancy column selection line thereof instead should be rapidly enabled. Simultaneously, a normal word line or a normal column pass should be rapidly enabled by a specific signal. Additionally, in a case where the address to enable the normal word line or the column pass in a next cycle is inputted after the enabled redundancy word line or the redundancy column pass performs its operation, a signal not selecting the normal word line or the column pass in a previous cycle should be rapidly enabled, thereby preventing a cell connected to the normal word line or the column pass from being selected at a low speed. Therefore, what is needed is a redundancy repair scheme which avoids an increase in signal load and does not slow the transition speed.